\hypertarget{structmmal__worker__port__param__get}{}\section{mmal\+\_\+worker\+\_\+port\+\_\+param\+\_\+get Struct Reference}
\label{structmmal__worker__port__param__get}\index{mmal\+\_\+worker\+\_\+port\+\_\+param\+\_\+get@{mmal\+\_\+worker\+\_\+port\+\_\+param\+\_\+get}}


{\ttfamily \#include $<$mmal\+\_\+vc\+\_\+msgs.\+h$>$}

\subsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\hypertarget{structmmal__worker__port__param__get_af41ace7e82e5b69789bd186d4df69200}{}\hyperlink{structmmal__worker__msg__header}{mmal\+\_\+worker\+\_\+msg\+\_\+header} {\bfseries header}\label{structmmal__worker__port__param__get_af41ace7e82e5b69789bd186d4df69200}

\item 
uint32\+\_\+t \hyperlink{structmmal__worker__port__param__get_a14075fa892ade12e161a51c1f7e03416}{component\+\_\+handle}
\item 
uint32\+\_\+t \hyperlink{structmmal__worker__port__param__get_a8aa1cc9a1e23be2055cfcdd63f82723f}{port\+\_\+handle}
\item 
\hyperlink{struct_m_m_a_l___p_a_r_a_m_e_t_e_r___h_e_a_d_e_r___t}{M\+M\+A\+L\+\_\+\+P\+A\+R\+A\+M\+E\+T\+E\+R\+\_\+\+H\+E\+A\+D\+E\+R\+\_\+\+T} \hyperlink{structmmal__worker__port__param__get_a967f9b307ab796f641e098eea6f21748}{param}
\item 
\hypertarget{structmmal__worker__port__param__get_af548b0594d9089d40c0f928f0231db30}{}uint32\+\_\+t {\bfseries space} \mbox{[}M\+M\+A\+L\+\_\+\+W\+O\+R\+K\+E\+R\+\_\+\+P\+O\+R\+T\+\_\+\+P\+A\+R\+A\+M\+E\+T\+E\+R\+\_\+\+S\+P\+A\+C\+E\mbox{]}\label{structmmal__worker__port__param__get_af548b0594d9089d40c0f928f0231db30}

\end{DoxyCompactItemize}


\subsection{Detailed Description}
Component port parameter get. 

\subsection{Member Data Documentation}
\hypertarget{structmmal__worker__port__param__get_a14075fa892ade12e161a51c1f7e03416}{}\index{mmal\+\_\+worker\+\_\+port\+\_\+param\+\_\+get@{mmal\+\_\+worker\+\_\+port\+\_\+param\+\_\+get}!component\+\_\+handle@{component\+\_\+handle}}
\index{component\+\_\+handle@{component\+\_\+handle}!mmal\+\_\+worker\+\_\+port\+\_\+param\+\_\+get@{mmal\+\_\+worker\+\_\+port\+\_\+param\+\_\+get}}
\subsubsection[{component\+\_\+handle}]{\setlength{\rightskip}{0pt plus 5cm}uint32\+\_\+t mmal\+\_\+worker\+\_\+port\+\_\+param\+\_\+get\+::component\+\_\+handle}\label{structmmal__worker__port__param__get_a14075fa892ade12e161a51c1f7e03416}
Which component \hypertarget{structmmal__worker__port__param__get_a967f9b307ab796f641e098eea6f21748}{}\index{mmal\+\_\+worker\+\_\+port\+\_\+param\+\_\+get@{mmal\+\_\+worker\+\_\+port\+\_\+param\+\_\+get}!param@{param}}
\index{param@{param}!mmal\+\_\+worker\+\_\+port\+\_\+param\+\_\+get@{mmal\+\_\+worker\+\_\+port\+\_\+param\+\_\+get}}
\subsubsection[{param}]{\setlength{\rightskip}{0pt plus 5cm}{\bf M\+M\+A\+L\+\_\+\+P\+A\+R\+A\+M\+E\+T\+E\+R\+\_\+\+H\+E\+A\+D\+E\+R\+\_\+\+T} mmal\+\_\+worker\+\_\+port\+\_\+param\+\_\+get\+::param}\label{structmmal__worker__port__param__get_a967f9b307ab796f641e098eea6f21748}
Parameter I\+D and size \hypertarget{structmmal__worker__port__param__get_a8aa1cc9a1e23be2055cfcdd63f82723f}{}\index{mmal\+\_\+worker\+\_\+port\+\_\+param\+\_\+get@{mmal\+\_\+worker\+\_\+port\+\_\+param\+\_\+get}!port\+\_\+handle@{port\+\_\+handle}}
\index{port\+\_\+handle@{port\+\_\+handle}!mmal\+\_\+worker\+\_\+port\+\_\+param\+\_\+get@{mmal\+\_\+worker\+\_\+port\+\_\+param\+\_\+get}}
\subsubsection[{port\+\_\+handle}]{\setlength{\rightskip}{0pt plus 5cm}uint32\+\_\+t mmal\+\_\+worker\+\_\+port\+\_\+param\+\_\+get\+::port\+\_\+handle}\label{structmmal__worker__port__param__get_a8aa1cc9a1e23be2055cfcdd63f82723f}
Which port 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
/\+Volumes/\+W\+O\+R\+K\+\_\+\+I\+N\+\_\+\+P\+R\+O\+G\+R\+E\+S\+S/\+R\+A\+S\+P\+B\+E\+R\+R\+Y\+\_\+\+P\+I/github/firmware-\/master/opt/vc/include/interface/mmal/vc/\hyperlink{mmal__vc__msgs_8h}{mmal\+\_\+vc\+\_\+msgs.\+h}\end{DoxyCompactItemize}
