\hypertarget{structmmal__worker__port__info__get}{}\section{mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+get Struct Reference}
\label{structmmal__worker__port__info__get}\index{mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+get@{mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+get}}


{\ttfamily \#include $<$mmal\+\_\+vc\+\_\+msgs.\+h$>$}

\subsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\hypertarget{structmmal__worker__port__info__get_a9568b97c0c3687e4adb5908a3b08e044}{}\hyperlink{structmmal__worker__msg__header}{mmal\+\_\+worker\+\_\+msg\+\_\+header} {\bfseries header}\label{structmmal__worker__port__info__get_a9568b97c0c3687e4adb5908a3b08e044}

\item 
uint32\+\_\+t \hyperlink{structmmal__worker__port__info__get_a37fc09739665ce145541f08311f2ff5b}{component\+\_\+handle}
\item 
\hyperlink{group___mmal_port_gafcd53d504d5e497ee9932be2aee0154a}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+T} \hyperlink{structmmal__worker__port__info__get_ae5bd107503d48360cc28a5c5f4812037}{port\+\_\+type}
\item 
uint32\+\_\+t \hyperlink{structmmal__worker__port__info__get_a74b11ffa44816f6cd4136bd0b70ecb25}{index}
\end{DoxyCompactItemize}


\subsection{Detailed Description}
Component port info. Used to get port info. 

\subsection{Member Data Documentation}
\hypertarget{structmmal__worker__port__info__get_a37fc09739665ce145541f08311f2ff5b}{}\index{mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+get@{mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+get}!component\+\_\+handle@{component\+\_\+handle}}
\index{component\+\_\+handle@{component\+\_\+handle}!mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+get@{mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+get}}
\subsubsection[{component\+\_\+handle}]{\setlength{\rightskip}{0pt plus 5cm}uint32\+\_\+t mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+get\+::component\+\_\+handle}\label{structmmal__worker__port__info__get_a37fc09739665ce145541f08311f2ff5b}
Which component \hypertarget{structmmal__worker__port__info__get_a74b11ffa44816f6cd4136bd0b70ecb25}{}\index{mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+get@{mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+get}!index@{index}}
\index{index@{index}!mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+get@{mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+get}}
\subsubsection[{index}]{\setlength{\rightskip}{0pt plus 5cm}uint32\+\_\+t mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+get\+::index}\label{structmmal__worker__port__info__get_a74b11ffa44816f6cd4136bd0b70ecb25}
Which port of given type to get \hypertarget{structmmal__worker__port__info__get_ae5bd107503d48360cc28a5c5f4812037}{}\index{mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+get@{mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+get}!port\+\_\+type@{port\+\_\+type}}
\index{port\+\_\+type@{port\+\_\+type}!mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+get@{mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+get}}
\subsubsection[{port\+\_\+type}]{\setlength{\rightskip}{0pt plus 5cm}{\bf M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+T} mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+get\+::port\+\_\+type}\label{structmmal__worker__port__info__get_ae5bd107503d48360cc28a5c5f4812037}
Type of port 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
/\+Volumes/\+W\+O\+R\+K\+\_\+\+I\+N\+\_\+\+P\+R\+O\+G\+R\+E\+S\+S/\+R\+A\+S\+P\+B\+E\+R\+R\+Y\+\_\+\+P\+I/github/firmware-\/master/opt/vc/include/interface/mmal/vc/\hyperlink{mmal__vc__msgs_8h}{mmal\+\_\+vc\+\_\+msgs.\+h}\end{DoxyCompactItemize}
