\hypertarget{structmmal__worker__event__to__host}{}\section{mmal\+\_\+worker\+\_\+event\+\_\+to\+\_\+host Struct Reference}
\label{structmmal__worker__event__to__host}\index{mmal\+\_\+worker\+\_\+event\+\_\+to\+\_\+host@{mmal\+\_\+worker\+\_\+event\+\_\+to\+\_\+host}}


{\ttfamily \#include $<$mmal\+\_\+vc\+\_\+msgs.\+h$>$}

\subsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\hypertarget{structmmal__worker__event__to__host_a3d7290a4d397a3ebb0586f482215d78a}{}\hyperlink{structmmal__worker__msg__header}{mmal\+\_\+worker\+\_\+msg\+\_\+header} {\bfseries header}\label{structmmal__worker__event__to__host_a3d7290a4d397a3ebb0586f482215d78a}

\item 
\hypertarget{structmmal__worker__event__to__host_a0a01db08a2820efad58088e367332ffd}{}struct \hyperlink{struct_m_m_a_l___c_o_m_p_o_n_e_n_t___t}{M\+M\+A\+L\+\_\+\+C\+O\+M\+P\+O\+N\+E\+N\+T\+\_\+\+T} $\ast$ {\bfseries client\+\_\+component}\label{structmmal__worker__event__to__host_a0a01db08a2820efad58088e367332ffd}

\item 
\hypertarget{structmmal__worker__event__to__host_a86e4099d91cc305474197e03aa4b44cd}{}uint32\+\_\+t {\bfseries port\+\_\+type}\label{structmmal__worker__event__to__host_a86e4099d91cc305474197e03aa4b44cd}

\item 
\hypertarget{structmmal__worker__event__to__host_a0d660d18023f2760f7fcbefb69058224}{}uint32\+\_\+t {\bfseries port\+\_\+num}\label{structmmal__worker__event__to__host_a0d660d18023f2760f7fcbefb69058224}

\item 
\hypertarget{structmmal__worker__event__to__host_afbdee52b85529982bf7489db54cfbc6b}{}uint32\+\_\+t {\bfseries cmd}\label{structmmal__worker__event__to__host_afbdee52b85529982bf7489db54cfbc6b}

\item 
\hypertarget{structmmal__worker__event__to__host_a889a22c33bb551043cd51c646d75c35c}{}uint32\+\_\+t {\bfseries length}\label{structmmal__worker__event__to__host_a889a22c33bb551043cd51c646d75c35c}

\item 
\hypertarget{structmmal__worker__event__to__host_a80b93c580dcdf2ce4e5e7a4d7c6d553c}{}uint8\+\_\+t {\bfseries data} \mbox{[}\hyperlink{mmal__vc__msgs_8h_a0926c949acdca7165c6d3be9b2eb5b8f}{M\+M\+A\+L\+\_\+\+W\+O\+R\+K\+E\+R\+\_\+\+E\+V\+E\+N\+T\+\_\+\+S\+P\+A\+C\+E}\mbox{]}\label{structmmal__worker__event__to__host_a80b93c580dcdf2ce4e5e7a4d7c6d553c}

\item 
\hypertarget{structmmal__worker__event__to__host_aa21d9313ea4d8ce4e1ce2509a39da9f8}{}\hyperlink{struct_m_m_a_l___b_u_f_f_e_r___h_e_a_d_e_r___t}{M\+M\+A\+L\+\_\+\+B\+U\+F\+F\+E\+R\+\_\+\+H\+E\+A\+D\+E\+R\+\_\+\+T} $\ast$ {\bfseries delayed\+\_\+buffer}\label{structmmal__worker__event__to__host_aa21d9313ea4d8ce4e1ce2509a39da9f8}

\end{DoxyCompactItemize}


\subsection{Detailed Description}
Send an event buffer from the host.

\begin{DoxySeeAlso}{See also}
mmal\+\_\+port\+\_\+send\+\_\+event() 
\end{DoxySeeAlso}


The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
/\+Volumes/\+W\+O\+R\+K\+\_\+\+I\+N\+\_\+\+P\+R\+O\+G\+R\+E\+S\+S/\+R\+A\+S\+P\+B\+E\+R\+R\+Y\+\_\+\+P\+I/github/firmware-\/master/opt/vc/include/interface/mmal/vc/\hyperlink{mmal__vc__msgs_8h}{mmal\+\_\+vc\+\_\+msgs.\+h}\end{DoxyCompactItemize}
