\hypertarget{structmmal__worker__port__info__set}{}\section{mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+set Struct Reference}
\label{structmmal__worker__port__info__set}\index{mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+set@{mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+set}}


{\ttfamily \#include $<$mmal\+\_\+vc\+\_\+msgs.\+h$>$}

\subsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\Hypertarget{structmmal__worker__port__info__set_ae3431f879eec4d561233bc17903ba1a3}\label{structmmal__worker__port__info__set_ae3431f879eec4d561233bc17903ba1a3}} 
\mbox{\hyperlink{structmmal__worker__msg__header}{mmal\+\_\+worker\+\_\+msg\+\_\+header}} {\bfseries header}
\item 
uint32\+\_\+t \mbox{\hyperlink{structmmal__worker__port__info__set_a86d2fc58c7aa58c17afc9b9df32fddb9}{component\+\_\+handle}}
\item 
\mbox{\hyperlink{group___mmal_port_gafcd53d504d5e497ee9932be2aee0154a}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+T}} \mbox{\hyperlink{structmmal__worker__port__info__set_a493c361e2ebf817750cdbcd026a308b1}{port\+\_\+type}}
\item 
uint32\+\_\+t \mbox{\hyperlink{structmmal__worker__port__info__set_a1b730b35641e48a614da9bdda4c753d8}{index}}
\item 
\mbox{\Hypertarget{structmmal__worker__port__info__set_ab0509b946204c3fc200cf689e3f06e55}\label{structmmal__worker__port__info__set_ab0509b946204c3fc200cf689e3f06e55}} 
\mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} {\bfseries port}
\item 
\mbox{\Hypertarget{structmmal__worker__port__info__set_a0257ebf547cf5634743513eac4a1ffe3}\label{structmmal__worker__port__info__set_a0257ebf547cf5634743513eac4a1ffe3}} 
\mbox{\hyperlink{struct_m_m_a_l___e_s___f_o_r_m_a_t___t}{M\+M\+A\+L\+\_\+\+E\+S\+\_\+\+F\+O\+R\+M\+A\+T\+\_\+T}} {\bfseries format}
\item 
\mbox{\Hypertarget{structmmal__worker__port__info__set_ac2c92bf586758b06355ba0551a2f87ba}\label{structmmal__worker__port__info__set_ac2c92bf586758b06355ba0551a2f87ba}} 
\mbox{\hyperlink{union_m_m_a_l___e_s___s_p_e_c_i_f_i_c___f_o_r_m_a_t___t}{M\+M\+A\+L\+\_\+\+E\+S\+\_\+\+S\+P\+E\+C\+I\+F\+I\+C\+\_\+\+F\+O\+R\+M\+A\+T\+\_\+T}} {\bfseries es}
\item 
\mbox{\Hypertarget{structmmal__worker__port__info__set_aa200f29b856f94fd78f2a036a2fb2369}\label{structmmal__worker__port__info__set_aa200f29b856f94fd78f2a036a2fb2369}} 
uint8\+\_\+t {\bfseries extradata} \mbox{[}\mbox{\hyperlink{mmal__vc__msgs_8h_a1dcbf385d0343125d54ac887d24f5e03}{M\+M\+A\+L\+\_\+\+F\+O\+R\+M\+A\+T\+\_\+\+E\+X\+T\+R\+A\+D\+A\+T\+A\+\_\+\+M\+A\+X\+\_\+\+S\+I\+ZE}}\mbox{]}
\end{DoxyCompactItemize}


\subsection{Detailed Description}
Component port info. Used to set port info. 

\subsection{Member Data Documentation}
\mbox{\Hypertarget{structmmal__worker__port__info__set_a86d2fc58c7aa58c17afc9b9df32fddb9}\label{structmmal__worker__port__info__set_a86d2fc58c7aa58c17afc9b9df32fddb9}} 
\index{mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+set@{mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+set}!component\+\_\+handle@{component\+\_\+handle}}
\index{component\+\_\+handle@{component\+\_\+handle}!mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+set@{mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+set}}
\subsubsection{\texorpdfstring{component\+\_\+handle}{component\_handle}}
{\footnotesize\ttfamily uint32\+\_\+t mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+set\+::component\+\_\+handle}

Which component \mbox{\Hypertarget{structmmal__worker__port__info__set_a1b730b35641e48a614da9bdda4c753d8}\label{structmmal__worker__port__info__set_a1b730b35641e48a614da9bdda4c753d8}} 
\index{mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+set@{mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+set}!index@{index}}
\index{index@{index}!mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+set@{mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+set}}
\subsubsection{\texorpdfstring{index}{index}}
{\footnotesize\ttfamily uint32\+\_\+t mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+set\+::index}

Which port of given type to get \mbox{\Hypertarget{structmmal__worker__port__info__set_a493c361e2ebf817750cdbcd026a308b1}\label{structmmal__worker__port__info__set_a493c361e2ebf817750cdbcd026a308b1}} 
\index{mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+set@{mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+set}!port\+\_\+type@{port\+\_\+type}}
\index{port\+\_\+type@{port\+\_\+type}!mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+set@{mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+set}}
\subsubsection{\texorpdfstring{port\+\_\+type}{port\_type}}
{\footnotesize\ttfamily \mbox{\hyperlink{group___mmal_port_gafcd53d504d5e497ee9932be2aee0154a}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+T}} mmal\+\_\+worker\+\_\+port\+\_\+info\+\_\+set\+::port\+\_\+type}

Type of port 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
/\+Volumes/\+W\+O\+R\+K\+\_\+\+I\+N\+\_\+\+P\+R\+O\+G\+R\+E\+S\+S/\+R\+A\+S\+P\+B\+E\+R\+R\+Y\+\_\+\+P\+I/firmware-\/master/opt/vc/include/interface/mmal/vc/\mbox{\hyperlink{mmal__vc__msgs_8h}{mmal\+\_\+vc\+\_\+msgs.\+h}}\end{DoxyCompactItemize}
