\hypertarget{group___mmal_port}{}\section{Ports}
\label{group___mmal_port}\index{Ports@{Ports}}
\subsection*{Classes}
\begin{DoxyCompactItemize}
\item 
struct \mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}}
\end{DoxyCompactItemize}
\subsection*{Typedefs}
\begin{DoxyCompactItemize}
\item 
typedef struct \mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} \mbox{\hyperlink{group___mmal_port_ga8c603079c9594da50cb74aa5f009e81f}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}}
\item 
typedef void($\ast$ \mbox{\hyperlink{group___mmal_port_ga9381e59b90628b9d5968fb18ed2b1cd9}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+B\+H\+\_\+\+C\+B\+\_\+T}}) (\mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} $\ast$port, \mbox{\hyperlink{struct_m_m_a_l___b_u_f_f_e_r___h_e_a_d_e_r___t}{M\+M\+A\+L\+\_\+\+B\+U\+F\+F\+E\+R\+\_\+\+H\+E\+A\+D\+E\+R\+\_\+T}} $\ast$buffer)
\end{DoxyCompactItemize}
\subsection*{Enumerations}
\begin{DoxyCompactItemize}
\item 
enum \mbox{\hyperlink{group___mmal_port_gafcd53d504d5e497ee9932be2aee0154a}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+T}} \{ \newline
\mbox{\hyperlink{group___mmal_port_ggafcd53d504d5e497ee9932be2aee0154aaa7cba36ec4ba3e2488a904b5072e386b}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+U\+N\+K\+N\+O\+WN}} = 0, 
\mbox{\hyperlink{group___mmal_port_ggafcd53d504d5e497ee9932be2aee0154aa925e293e4179240c736c03d06623f292}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+C\+O\+N\+T\+R\+OL}}, 
\mbox{\hyperlink{group___mmal_port_ggafcd53d504d5e497ee9932be2aee0154aab41b6faf1f49e1445642d1439ca2336d}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+I\+N\+P\+UT}}, 
\mbox{\hyperlink{group___mmal_port_ggafcd53d504d5e497ee9932be2aee0154aa0c74e9ab168532decc87be178d047b7c}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+O\+U\+T\+P\+UT}}, 
\newline
\mbox{\hyperlink{group___mmal_port_ggafcd53d504d5e497ee9932be2aee0154aa6e44c890cfbec5ee4f964b3c422d2da1}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+C\+L\+O\+CK}}, 
\mbox{\hyperlink{group___mmal_port_ggafcd53d504d5e497ee9932be2aee0154aa26cea74e887a408a59fa63467cc3c5b5}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+I\+N\+V\+A\+L\+ID}} = 0xffffffff
 \}
\end{DoxyCompactItemize}
\subsection*{Functions}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{group___mmal_types_ga5ac87230bd615d2b154a9d5899bc37fd}{M\+M\+A\+L\+\_\+\+S\+T\+A\+T\+U\+S\+\_\+T}} \mbox{\hyperlink{group___mmal_port_gae118f5d30974f414fd2ead7891ad9ee9}{mmal\+\_\+port\+\_\+format\+\_\+commit}} (\mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} $\ast$port)
\item 
\mbox{\hyperlink{group___mmal_types_ga5ac87230bd615d2b154a9d5899bc37fd}{M\+M\+A\+L\+\_\+\+S\+T\+A\+T\+U\+S\+\_\+T}} \mbox{\hyperlink{group___mmal_port_gaa723c325260a53f553c6ab7ee8038b70}{mmal\+\_\+port\+\_\+enable}} (\mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} $\ast$port, \mbox{\hyperlink{group___mmal_port_ga9381e59b90628b9d5968fb18ed2b1cd9}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+B\+H\+\_\+\+C\+B\+\_\+T}} cb)
\item 
\mbox{\hyperlink{group___mmal_types_ga5ac87230bd615d2b154a9d5899bc37fd}{M\+M\+A\+L\+\_\+\+S\+T\+A\+T\+U\+S\+\_\+T}} \mbox{\hyperlink{group___mmal_port_ga28ba868d23823323340b83499a4992d8}{mmal\+\_\+port\+\_\+disable}} (\mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} $\ast$port)
\item 
\mbox{\hyperlink{group___mmal_types_ga5ac87230bd615d2b154a9d5899bc37fd}{M\+M\+A\+L\+\_\+\+S\+T\+A\+T\+U\+S\+\_\+T}} \mbox{\hyperlink{group___mmal_port_ga3855570ad4aab2b5761fd5897b7b3780}{mmal\+\_\+port\+\_\+flush}} (\mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} $\ast$port)
\item 
\mbox{\hyperlink{group___mmal_types_ga5ac87230bd615d2b154a9d5899bc37fd}{M\+M\+A\+L\+\_\+\+S\+T\+A\+T\+U\+S\+\_\+T}} \mbox{\hyperlink{group___mmal_port_ga7feccb996f0bab5c798b3465747bb0a3}{mmal\+\_\+port\+\_\+parameter\+\_\+set}} (\mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} $\ast$port, const \mbox{\hyperlink{struct_m_m_a_l___p_a_r_a_m_e_t_e_r___h_e_a_d_e_r___t}{M\+M\+A\+L\+\_\+\+P\+A\+R\+A\+M\+E\+T\+E\+R\+\_\+\+H\+E\+A\+D\+E\+R\+\_\+T}} $\ast$param)
\item 
\mbox{\hyperlink{group___mmal_types_ga5ac87230bd615d2b154a9d5899bc37fd}{M\+M\+A\+L\+\_\+\+S\+T\+A\+T\+U\+S\+\_\+T}} \mbox{\hyperlink{group___mmal_port_ga58f2b79985132199992a99790264541a}{mmal\+\_\+port\+\_\+parameter\+\_\+get}} (\mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} $\ast$port, \mbox{\hyperlink{struct_m_m_a_l___p_a_r_a_m_e_t_e_r___h_e_a_d_e_r___t}{M\+M\+A\+L\+\_\+\+P\+A\+R\+A\+M\+E\+T\+E\+R\+\_\+\+H\+E\+A\+D\+E\+R\+\_\+T}} $\ast$param)
\item 
\mbox{\hyperlink{group___mmal_types_ga5ac87230bd615d2b154a9d5899bc37fd}{M\+M\+A\+L\+\_\+\+S\+T\+A\+T\+U\+S\+\_\+T}} \mbox{\hyperlink{group___mmal_port_ga098a7b91bb6fc596aed0e5585aee3253}{mmal\+\_\+port\+\_\+send\+\_\+buffer}} (\mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} $\ast$port, \mbox{\hyperlink{struct_m_m_a_l___b_u_f_f_e_r___h_e_a_d_e_r___t}{M\+M\+A\+L\+\_\+\+B\+U\+F\+F\+E\+R\+\_\+\+H\+E\+A\+D\+E\+R\+\_\+T}} $\ast$buffer)
\item 
\mbox{\hyperlink{group___mmal_types_ga5ac87230bd615d2b154a9d5899bc37fd}{M\+M\+A\+L\+\_\+\+S\+T\+A\+T\+U\+S\+\_\+T}} \mbox{\hyperlink{group___mmal_port_ga0cdb2f64bfe45e79e3b8871e64111ee4}{mmal\+\_\+port\+\_\+connect}} (\mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} $\ast$port, \mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} $\ast$other\+\_\+port)
\item 
\mbox{\hyperlink{group___mmal_types_ga5ac87230bd615d2b154a9d5899bc37fd}{M\+M\+A\+L\+\_\+\+S\+T\+A\+T\+U\+S\+\_\+T}} \mbox{\hyperlink{group___mmal_port_ga195a97ebd206bed9c9d3d1d647610cbb}{mmal\+\_\+port\+\_\+disconnect}} (\mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} $\ast$port)
\item 
uint8\+\_\+t $\ast$ \mbox{\hyperlink{group___mmal_port_ga24fe58a6e95a5d69f79e1b69a601b714}{mmal\+\_\+port\+\_\+payload\+\_\+alloc}} (\mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} $\ast$port, uint32\+\_\+t payload\+\_\+size)
\item 
void \mbox{\hyperlink{group___mmal_port_gac130ad58018b781b0522a015bd243801}{mmal\+\_\+port\+\_\+payload\+\_\+free}} (\mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} $\ast$port, uint8\+\_\+t $\ast$payload)
\item 
\mbox{\hyperlink{group___mmal_types_ga5ac87230bd615d2b154a9d5899bc37fd}{M\+M\+A\+L\+\_\+\+S\+T\+A\+T\+U\+S\+\_\+T}} \mbox{\hyperlink{group___mmal_port_ga2dc6f1939e26c7fdd46485ba1744bd55}{mmal\+\_\+port\+\_\+event\+\_\+get}} (\mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} $\ast$port, \mbox{\hyperlink{struct_m_m_a_l___b_u_f_f_e_r___h_e_a_d_e_r___t}{M\+M\+A\+L\+\_\+\+B\+U\+F\+F\+E\+R\+\_\+\+H\+E\+A\+D\+E\+R\+\_\+T}} $\ast$$\ast$buffer, uint32\+\_\+t event)
\end{DoxyCompactItemize}
\subsection*{Port capabilities}
\label{_amgrp7b575f11039e7ac01218f25e505a4f3a}%
\label{group___mmal_port_portcapabilities}%
\Hypertarget{group___mmal_port_portcapabilities}%
The following flags describe the capabilities advertised by a port \begin{DoxyCompactItemize}
\item 
\#define \mbox{\hyperlink{group___mmal_port_ga2322087d73a273054f0f71ca641a2831}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+C\+A\+P\+A\+B\+I\+L\+I\+T\+Y\+\_\+\+P\+A\+S\+S\+T\+H\+R\+O\+U\+GH}}~0x01
\item 
\#define \mbox{\hyperlink{group___mmal_port_ga8c18cef2b86265f8c52d506040b2119c}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+C\+A\+P\+A\+B\+I\+L\+I\+T\+Y\+\_\+\+A\+L\+L\+O\+C\+A\+T\+I\+ON}}~0x02
\item 
\#define \mbox{\hyperlink{group___mmal_port_gaab1f67c204d28ba5a9eaa437748c2a30}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+C\+A\+P\+A\+B\+I\+L\+I\+T\+Y\+\_\+\+S\+U\+P\+P\+O\+R\+T\+S\+\_\+\+E\+V\+E\+N\+T\+\_\+\+F\+O\+R\+M\+A\+T\+\_\+\+C\+H\+A\+N\+GE}}~0x04
\end{DoxyCompactItemize}


\subsection{Detailed Description}
Definition of a M\+M\+AL port and its associated A\+PI 

\subsection{Macro Definition Documentation}
\mbox{\Hypertarget{group___mmal_port_ga8c18cef2b86265f8c52d506040b2119c}\label{group___mmal_port_ga8c18cef2b86265f8c52d506040b2119c}} 
\index{Ports@{Ports}!M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+C\+A\+P\+A\+B\+I\+L\+I\+T\+Y\+\_\+\+A\+L\+L\+O\+C\+A\+T\+I\+ON@{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+C\+A\+P\+A\+B\+I\+L\+I\+T\+Y\+\_\+\+A\+L\+L\+O\+C\+A\+T\+I\+ON}}
\index{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+C\+A\+P\+A\+B\+I\+L\+I\+T\+Y\+\_\+\+A\+L\+L\+O\+C\+A\+T\+I\+ON@{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+C\+A\+P\+A\+B\+I\+L\+I\+T\+Y\+\_\+\+A\+L\+L\+O\+C\+A\+T\+I\+ON}!Ports@{Ports}}
\subsubsection{\texorpdfstring{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+C\+A\+P\+A\+B\+I\+L\+I\+T\+Y\+\_\+\+A\+L\+L\+O\+C\+A\+T\+I\+ON}{MMAL\_PORT\_CAPABILITY\_ALLOCATION}}
{\footnotesize\ttfamily \#define M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+C\+A\+P\+A\+B\+I\+L\+I\+T\+Y\+\_\+\+A\+L\+L\+O\+C\+A\+T\+I\+ON~0x02}

The port wants to allocate the buffer payloads. This signals a preference that payload allocation should be done on this port for efficiency reasons. \mbox{\Hypertarget{group___mmal_port_ga2322087d73a273054f0f71ca641a2831}\label{group___mmal_port_ga2322087d73a273054f0f71ca641a2831}} 
\index{Ports@{Ports}!M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+C\+A\+P\+A\+B\+I\+L\+I\+T\+Y\+\_\+\+P\+A\+S\+S\+T\+H\+R\+O\+U\+GH@{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+C\+A\+P\+A\+B\+I\+L\+I\+T\+Y\+\_\+\+P\+A\+S\+S\+T\+H\+R\+O\+U\+GH}}
\index{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+C\+A\+P\+A\+B\+I\+L\+I\+T\+Y\+\_\+\+P\+A\+S\+S\+T\+H\+R\+O\+U\+GH@{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+C\+A\+P\+A\+B\+I\+L\+I\+T\+Y\+\_\+\+P\+A\+S\+S\+T\+H\+R\+O\+U\+GH}!Ports@{Ports}}
\subsubsection{\texorpdfstring{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+C\+A\+P\+A\+B\+I\+L\+I\+T\+Y\+\_\+\+P\+A\+S\+S\+T\+H\+R\+O\+U\+GH}{MMAL\_PORT\_CAPABILITY\_PASSTHROUGH}}
{\footnotesize\ttfamily \#define M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+C\+A\+P\+A\+B\+I\+L\+I\+T\+Y\+\_\+\+P\+A\+S\+S\+T\+H\+R\+O\+U\+GH~0x01}

The port is pass-\/through and doesn\textquotesingle{}t need buffer headers allocated \mbox{\Hypertarget{group___mmal_port_gaab1f67c204d28ba5a9eaa437748c2a30}\label{group___mmal_port_gaab1f67c204d28ba5a9eaa437748c2a30}} 
\index{Ports@{Ports}!M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+C\+A\+P\+A\+B\+I\+L\+I\+T\+Y\+\_\+\+S\+U\+P\+P\+O\+R\+T\+S\+\_\+\+E\+V\+E\+N\+T\+\_\+\+F\+O\+R\+M\+A\+T\+\_\+\+C\+H\+A\+N\+GE@{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+C\+A\+P\+A\+B\+I\+L\+I\+T\+Y\+\_\+\+S\+U\+P\+P\+O\+R\+T\+S\+\_\+\+E\+V\+E\+N\+T\+\_\+\+F\+O\+R\+M\+A\+T\+\_\+\+C\+H\+A\+N\+GE}}
\index{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+C\+A\+P\+A\+B\+I\+L\+I\+T\+Y\+\_\+\+S\+U\+P\+P\+O\+R\+T\+S\+\_\+\+E\+V\+E\+N\+T\+\_\+\+F\+O\+R\+M\+A\+T\+\_\+\+C\+H\+A\+N\+GE@{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+C\+A\+P\+A\+B\+I\+L\+I\+T\+Y\+\_\+\+S\+U\+P\+P\+O\+R\+T\+S\+\_\+\+E\+V\+E\+N\+T\+\_\+\+F\+O\+R\+M\+A\+T\+\_\+\+C\+H\+A\+N\+GE}!Ports@{Ports}}
\subsubsection{\texorpdfstring{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+C\+A\+P\+A\+B\+I\+L\+I\+T\+Y\+\_\+\+S\+U\+P\+P\+O\+R\+T\+S\+\_\+\+E\+V\+E\+N\+T\+\_\+\+F\+O\+R\+M\+A\+T\+\_\+\+C\+H\+A\+N\+GE}{MMAL\_PORT\_CAPABILITY\_SUPPORTS\_EVENT\_FORMAT\_CHANGE}}
{\footnotesize\ttfamily \#define M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+C\+A\+P\+A\+B\+I\+L\+I\+T\+Y\+\_\+\+S\+U\+P\+P\+O\+R\+T\+S\+\_\+\+E\+V\+E\+N\+T\+\_\+\+F\+O\+R\+M\+A\+T\+\_\+\+C\+H\+A\+N\+GE~0x04}

The port supports format change events. This applies to input ports and is used to let the client know whether the port supports being reconfigured via a format change event (i.\+e. without having to disable the port). 

\subsection{Typedef Documentation}
\mbox{\Hypertarget{group___mmal_port_ga9381e59b90628b9d5968fb18ed2b1cd9}\label{group___mmal_port_ga9381e59b90628b9d5968fb18ed2b1cd9}} 
\index{Ports@{Ports}!M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+B\+H\+\_\+\+C\+B\+\_\+T@{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+B\+H\+\_\+\+C\+B\+\_\+T}}
\index{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+B\+H\+\_\+\+C\+B\+\_\+T@{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+B\+H\+\_\+\+C\+B\+\_\+T}!Ports@{Ports}}
\subsubsection{\texorpdfstring{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+B\+H\+\_\+\+C\+B\+\_\+T}{MMAL\_PORT\_BH\_CB\_T}}
{\footnotesize\ttfamily typedef void($\ast$ M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+B\+H\+\_\+\+C\+B\+\_\+T) (\mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} $\ast$port, \mbox{\hyperlink{struct_m_m_a_l___b_u_f_f_e_r___h_e_a_d_e_r___t}{M\+M\+A\+L\+\_\+\+B\+U\+F\+F\+E\+R\+\_\+\+H\+E\+A\+D\+E\+R\+\_\+T}} $\ast$buffer)}

Definition of the callback used by a port to send a \mbox{\hyperlink{struct_m_m_a_l___b_u_f_f_e_r___h_e_a_d_e_r___t}{M\+M\+A\+L\+\_\+\+B\+U\+F\+F\+E\+R\+\_\+\+H\+E\+A\+D\+E\+R\+\_\+T}} back to the user.


\begin{DoxyParams}{Parameters}
{\em port} & The port sending the buffer header. \\
\hline
{\em buffer} & The buffer header being sent. \\
\hline
\end{DoxyParams}
\mbox{\Hypertarget{group___mmal_port_ga8c603079c9594da50cb74aa5f009e81f}\label{group___mmal_port_ga8c603079c9594da50cb74aa5f009e81f}} 
\index{Ports@{Ports}!M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T@{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}}
\index{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T@{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}!Ports@{Ports}}
\subsubsection{\texorpdfstring{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}{MMAL\_PORT\_T}}
{\footnotesize\ttfamily typedef struct \mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}}  \mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}}}

Definition of a port. A port is the entity that is exposed by components to receive or transmit buffer headers (\mbox{\hyperlink{struct_m_m_a_l___b_u_f_f_e_r___h_e_a_d_e_r___t}{M\+M\+A\+L\+\_\+\+B\+U\+F\+F\+E\+R\+\_\+\+H\+E\+A\+D\+E\+R\+\_\+T}}). A port is defined by its \mbox{\hyperlink{struct_m_m_a_l___e_s___f_o_r_m_a_t___t}{M\+M\+A\+L\+\_\+\+E\+S\+\_\+\+F\+O\+R\+M\+A\+T\+\_\+T}}.

It may be possible to override the buffer requirements of a port by using the M\+M\+A\+L\+\_\+\+P\+A\+R\+A\+M\+E\+T\+E\+R\+\_\+\+B\+U\+F\+F\+E\+R\+\_\+\+R\+E\+Q\+U\+I\+R\+E\+M\+E\+N\+TS parameter. 

\subsection{Enumeration Type Documentation}
\mbox{\Hypertarget{group___mmal_port_gafcd53d504d5e497ee9932be2aee0154a}\label{group___mmal_port_gafcd53d504d5e497ee9932be2aee0154a}} 
\index{Ports@{Ports}!M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+T@{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+T}}
\index{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+T@{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+T}!Ports@{Ports}}
\subsubsection{\texorpdfstring{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+T}{MMAL\_PORT\_TYPE\_T}}
{\footnotesize\ttfamily enum \mbox{\hyperlink{group___mmal_port_gafcd53d504d5e497ee9932be2aee0154a}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+T}}}

List of port types \begin{DoxyEnumFields}{Enumerator}
\raisebox{\heightof{T}}[0pt][0pt]{\index{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+U\+N\+K\+N\+O\+WN@{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+U\+N\+K\+N\+O\+WN}!Ports@{Ports}}\index{Ports@{Ports}!M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+U\+N\+K\+N\+O\+WN@{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+U\+N\+K\+N\+O\+WN}}}\mbox{\Hypertarget{group___mmal_port_ggafcd53d504d5e497ee9932be2aee0154aaa7cba36ec4ba3e2488a904b5072e386b}\label{group___mmal_port_ggafcd53d504d5e497ee9932be2aee0154aaa7cba36ec4ba3e2488a904b5072e386b}} 
M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+U\+N\+K\+N\+O\+WN&Unknown port type \\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+C\+O\+N\+T\+R\+OL@{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+C\+O\+N\+T\+R\+OL}!Ports@{Ports}}\index{Ports@{Ports}!M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+C\+O\+N\+T\+R\+OL@{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+C\+O\+N\+T\+R\+OL}}}\mbox{\Hypertarget{group___mmal_port_ggafcd53d504d5e497ee9932be2aee0154aa925e293e4179240c736c03d06623f292}\label{group___mmal_port_ggafcd53d504d5e497ee9932be2aee0154aa925e293e4179240c736c03d06623f292}} 
M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+C\+O\+N\+T\+R\+OL&Control port \\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+I\+N\+P\+UT@{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+I\+N\+P\+UT}!Ports@{Ports}}\index{Ports@{Ports}!M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+I\+N\+P\+UT@{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+I\+N\+P\+UT}}}\mbox{\Hypertarget{group___mmal_port_ggafcd53d504d5e497ee9932be2aee0154aab41b6faf1f49e1445642d1439ca2336d}\label{group___mmal_port_ggafcd53d504d5e497ee9932be2aee0154aab41b6faf1f49e1445642d1439ca2336d}} 
M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+I\+N\+P\+UT&Input port \\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+O\+U\+T\+P\+UT@{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+O\+U\+T\+P\+UT}!Ports@{Ports}}\index{Ports@{Ports}!M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+O\+U\+T\+P\+UT@{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+O\+U\+T\+P\+UT}}}\mbox{\Hypertarget{group___mmal_port_ggafcd53d504d5e497ee9932be2aee0154aa0c74e9ab168532decc87be178d047b7c}\label{group___mmal_port_ggafcd53d504d5e497ee9932be2aee0154aa0c74e9ab168532decc87be178d047b7c}} 
M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+O\+U\+T\+P\+UT&Output port \\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+C\+L\+O\+CK@{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+C\+L\+O\+CK}!Ports@{Ports}}\index{Ports@{Ports}!M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+C\+L\+O\+CK@{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+C\+L\+O\+CK}}}\mbox{\Hypertarget{group___mmal_port_ggafcd53d504d5e497ee9932be2aee0154aa6e44c890cfbec5ee4f964b3c422d2da1}\label{group___mmal_port_ggafcd53d504d5e497ee9932be2aee0154aa6e44c890cfbec5ee4f964b3c422d2da1}} 
M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+C\+L\+O\+CK&Clock port \\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+I\+N\+V\+A\+L\+ID@{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+I\+N\+V\+A\+L\+ID}!Ports@{Ports}}\index{Ports@{Ports}!M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+I\+N\+V\+A\+L\+ID@{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+I\+N\+V\+A\+L\+ID}}}\mbox{\Hypertarget{group___mmal_port_ggafcd53d504d5e497ee9932be2aee0154aa26cea74e887a408a59fa63467cc3c5b5}\label{group___mmal_port_ggafcd53d504d5e497ee9932be2aee0154aa26cea74e887a408a59fa63467cc3c5b5}} 
M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+T\+Y\+P\+E\+\_\+\+I\+N\+V\+A\+L\+ID&Dummy value to force 32bit enum \\
\hline

\end{DoxyEnumFields}


\subsection{Function Documentation}
\mbox{\Hypertarget{group___mmal_port_ga0cdb2f64bfe45e79e3b8871e64111ee4}\label{group___mmal_port_ga0cdb2f64bfe45e79e3b8871e64111ee4}} 
\index{Ports@{Ports}!mmal\+\_\+port\+\_\+connect@{mmal\+\_\+port\+\_\+connect}}
\index{mmal\+\_\+port\+\_\+connect@{mmal\+\_\+port\+\_\+connect}!Ports@{Ports}}
\subsubsection{\texorpdfstring{mmal\+\_\+port\+\_\+connect()}{mmal\_port\_connect()}}
{\footnotesize\ttfamily \mbox{\hyperlink{group___mmal_types_ga5ac87230bd615d2b154a9d5899bc37fd}{M\+M\+A\+L\+\_\+\+S\+T\+A\+T\+U\+S\+\_\+T}} mmal\+\_\+port\+\_\+connect (\begin{DoxyParamCaption}\item[{\mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} $\ast$}]{port,  }\item[{\mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} $\ast$}]{other\+\_\+port }\end{DoxyParamCaption})}

Connect an output port to an input port.

When connected and enabled, buffers will automatically progress from the output port to the input port when they become available, and released back to the output port when no longer required by the input port.

Ports can be given either way around, but one must be an output port and the other must be an input port. Neither can be connected or enabled already. The format of the output port will be applied to the input port on connection.


\begin{DoxyParams}{Parameters}
{\em port} & One of the ports to connect. \\
\hline
{\em other\+\_\+port} & The other port to connect. \\
\hline
\end{DoxyParams}
\begin{DoxyReturn}{Returns}
M\+M\+A\+L\+\_\+\+S\+U\+C\+C\+E\+SS on success. 
\end{DoxyReturn}
\mbox{\Hypertarget{group___mmal_port_ga28ba868d23823323340b83499a4992d8}\label{group___mmal_port_ga28ba868d23823323340b83499a4992d8}} 
\index{Ports@{Ports}!mmal\+\_\+port\+\_\+disable@{mmal\+\_\+port\+\_\+disable}}
\index{mmal\+\_\+port\+\_\+disable@{mmal\+\_\+port\+\_\+disable}!Ports@{Ports}}
\subsubsection{\texorpdfstring{mmal\+\_\+port\+\_\+disable()}{mmal\_port\_disable()}}
{\footnotesize\ttfamily \mbox{\hyperlink{group___mmal_types_ga5ac87230bd615d2b154a9d5899bc37fd}{M\+M\+A\+L\+\_\+\+S\+T\+A\+T\+U\+S\+\_\+T}} mmal\+\_\+port\+\_\+disable (\begin{DoxyParamCaption}\item[{\mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} $\ast$}]{port }\end{DoxyParamCaption})}

Disable processing on a port

Disabling a port will stop all processing on this port and return all (non-\/processed) buffer headers to the client.

If this is a connected output port, the input port to which it is connected shall also be disabled. Any buffer pool shall be released.


\begin{DoxyParams}{Parameters}
{\em port} & port to disable \\
\hline
\end{DoxyParams}
\begin{DoxyReturn}{Returns}
M\+M\+A\+L\+\_\+\+S\+U\+C\+C\+E\+SS on success 
\end{DoxyReturn}
\mbox{\Hypertarget{group___mmal_port_ga195a97ebd206bed9c9d3d1d647610cbb}\label{group___mmal_port_ga195a97ebd206bed9c9d3d1d647610cbb}} 
\index{Ports@{Ports}!mmal\+\_\+port\+\_\+disconnect@{mmal\+\_\+port\+\_\+disconnect}}
\index{mmal\+\_\+port\+\_\+disconnect@{mmal\+\_\+port\+\_\+disconnect}!Ports@{Ports}}
\subsubsection{\texorpdfstring{mmal\+\_\+port\+\_\+disconnect()}{mmal\_port\_disconnect()}}
{\footnotesize\ttfamily \mbox{\hyperlink{group___mmal_types_ga5ac87230bd615d2b154a9d5899bc37fd}{M\+M\+A\+L\+\_\+\+S\+T\+A\+T\+U\+S\+\_\+T}} mmal\+\_\+port\+\_\+disconnect (\begin{DoxyParamCaption}\item[{\mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} $\ast$}]{port }\end{DoxyParamCaption})}

Disconnect a connected port.

If the port is not connected, an error will be returned. Otherwise, if the ports are enabled, they will be disabled and any buffer pool created will be freed.


\begin{DoxyParams}{Parameters}
{\em port} & The ports to disconnect. \\
\hline
\end{DoxyParams}
\begin{DoxyReturn}{Returns}
M\+M\+A\+L\+\_\+\+S\+U\+C\+C\+E\+SS on success. 
\end{DoxyReturn}
\mbox{\Hypertarget{group___mmal_port_gaa723c325260a53f553c6ab7ee8038b70}\label{group___mmal_port_gaa723c325260a53f553c6ab7ee8038b70}} 
\index{Ports@{Ports}!mmal\+\_\+port\+\_\+enable@{mmal\+\_\+port\+\_\+enable}}
\index{mmal\+\_\+port\+\_\+enable@{mmal\+\_\+port\+\_\+enable}!Ports@{Ports}}
\subsubsection{\texorpdfstring{mmal\+\_\+port\+\_\+enable()}{mmal\_port\_enable()}}
{\footnotesize\ttfamily \mbox{\hyperlink{group___mmal_types_ga5ac87230bd615d2b154a9d5899bc37fd}{M\+M\+A\+L\+\_\+\+S\+T\+A\+T\+U\+S\+\_\+T}} mmal\+\_\+port\+\_\+enable (\begin{DoxyParamCaption}\item[{\mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} $\ast$}]{port,  }\item[{\mbox{\hyperlink{group___mmal_port_ga9381e59b90628b9d5968fb18ed2b1cd9}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+\+B\+H\+\_\+\+C\+B\+\_\+T}}}]{cb }\end{DoxyParamCaption})}

Enable processing on a port

If this port is connected to another, the given callback must be N\+U\+LL, while for a disconnected port, the callback must be non-\/\+N\+U\+LL.

If this is a connected output port and is successfully enabled\+: 
\begin{DoxyItemize}
\item The port shall be populated with a pool of buffers, allocated as required, according to the buffer\+\_\+num and buffer\+\_\+size values. 
\item The input port to which it is connected shall be set to the same buffer configuration and then be enabled. Should that fail, the original port shall be disabled. 
\end{DoxyItemize}


\begin{DoxyParams}{Parameters}
{\em port} & port to enable \\
\hline
{\em cb} & callback use by the port to send a \mbox{\hyperlink{struct_m_m_a_l___b_u_f_f_e_r___h_e_a_d_e_r___t}{M\+M\+A\+L\+\_\+\+B\+U\+F\+F\+E\+R\+\_\+\+H\+E\+A\+D\+E\+R\+\_\+T}} back \\
\hline
\end{DoxyParams}
\begin{DoxyReturn}{Returns}
M\+M\+A\+L\+\_\+\+S\+U\+C\+C\+E\+SS on success 
\end{DoxyReturn}
\mbox{\Hypertarget{group___mmal_port_ga2dc6f1939e26c7fdd46485ba1744bd55}\label{group___mmal_port_ga2dc6f1939e26c7fdd46485ba1744bd55}} 
\index{Ports@{Ports}!mmal\+\_\+port\+\_\+event\+\_\+get@{mmal\+\_\+port\+\_\+event\+\_\+get}}
\index{mmal\+\_\+port\+\_\+event\+\_\+get@{mmal\+\_\+port\+\_\+event\+\_\+get}!Ports@{Ports}}
\subsubsection{\texorpdfstring{mmal\+\_\+port\+\_\+event\+\_\+get()}{mmal\_port\_event\_get()}}
{\footnotesize\ttfamily \mbox{\hyperlink{group___mmal_types_ga5ac87230bd615d2b154a9d5899bc37fd}{M\+M\+A\+L\+\_\+\+S\+T\+A\+T\+U\+S\+\_\+T}} mmal\+\_\+port\+\_\+event\+\_\+get (\begin{DoxyParamCaption}\item[{\mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} $\ast$}]{port,  }\item[{\mbox{\hyperlink{struct_m_m_a_l___b_u_f_f_e_r___h_e_a_d_e_r___t}{M\+M\+A\+L\+\_\+\+B\+U\+F\+F\+E\+R\+\_\+\+H\+E\+A\+D\+E\+R\+\_\+T}} $\ast$$\ast$}]{buffer,  }\item[{uint32\+\_\+t}]{event }\end{DoxyParamCaption})}

Get an empty event buffer header from a port


\begin{DoxyParams}{Parameters}
{\em port} & The port from which to get the event buffer header. \\
\hline
{\em buffer} & The address of a buffer header pointer, which will be set on return. \\
\hline
{\em event} & The specific event Four\+CC required. See the \mbox{\hyperlink{group___mmal_events}{pre-\/defined events}}. \\
\hline
\end{DoxyParams}
\begin{DoxyReturn}{Returns}
M\+M\+A\+L\+\_\+\+S\+U\+C\+C\+E\+SS on success 
\end{DoxyReturn}
\mbox{\Hypertarget{group___mmal_port_ga3855570ad4aab2b5761fd5897b7b3780}\label{group___mmal_port_ga3855570ad4aab2b5761fd5897b7b3780}} 
\index{Ports@{Ports}!mmal\+\_\+port\+\_\+flush@{mmal\+\_\+port\+\_\+flush}}
\index{mmal\+\_\+port\+\_\+flush@{mmal\+\_\+port\+\_\+flush}!Ports@{Ports}}
\subsubsection{\texorpdfstring{mmal\+\_\+port\+\_\+flush()}{mmal\_port\_flush()}}
{\footnotesize\ttfamily \mbox{\hyperlink{group___mmal_types_ga5ac87230bd615d2b154a9d5899bc37fd}{M\+M\+A\+L\+\_\+\+S\+T\+A\+T\+U\+S\+\_\+T}} mmal\+\_\+port\+\_\+flush (\begin{DoxyParamCaption}\item[{\mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} $\ast$}]{port }\end{DoxyParamCaption})}

Ask a port to release all the buffer headers it currently has.

Flushing a port will ask the port to send all the buffer headers it currently has to the client. Flushing is an asynchronous request and the flush call will return before all the buffer headers are returned to the client. It is up to the client to keep a count on the buffer headers to know when the flush operation has completed. It is also important to note that flushing will also reset the state of the port and any processing which was buffered by the port will be lost.

\begin{DoxyAttention}{Attention}
Flushing a connected port behaviour T\+BD.
\end{DoxyAttention}

\begin{DoxyParams}{Parameters}
{\em port} & The port to flush. \\
\hline
\end{DoxyParams}
\begin{DoxyReturn}{Returns}
M\+M\+A\+L\+\_\+\+S\+U\+C\+C\+E\+SS on success 
\end{DoxyReturn}
\mbox{\Hypertarget{group___mmal_port_gae118f5d30974f414fd2ead7891ad9ee9}\label{group___mmal_port_gae118f5d30974f414fd2ead7891ad9ee9}} 
\index{Ports@{Ports}!mmal\+\_\+port\+\_\+format\+\_\+commit@{mmal\+\_\+port\+\_\+format\+\_\+commit}}
\index{mmal\+\_\+port\+\_\+format\+\_\+commit@{mmal\+\_\+port\+\_\+format\+\_\+commit}!Ports@{Ports}}
\subsubsection{\texorpdfstring{mmal\+\_\+port\+\_\+format\+\_\+commit()}{mmal\_port\_format\_commit()}}
{\footnotesize\ttfamily \mbox{\hyperlink{group___mmal_types_ga5ac87230bd615d2b154a9d5899bc37fd}{M\+M\+A\+L\+\_\+\+S\+T\+A\+T\+U\+S\+\_\+T}} mmal\+\_\+port\+\_\+format\+\_\+commit (\begin{DoxyParamCaption}\item[{\mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} $\ast$}]{port }\end{DoxyParamCaption})}

Commit format changes on a port.


\begin{DoxyParams}{Parameters}
{\em port} & The port for which format changes are to be committed. \\
\hline
\end{DoxyParams}
\begin{DoxyReturn}{Returns}
M\+M\+A\+L\+\_\+\+S\+U\+C\+C\+E\+SS on success 
\end{DoxyReturn}
\mbox{\Hypertarget{group___mmal_port_ga58f2b79985132199992a99790264541a}\label{group___mmal_port_ga58f2b79985132199992a99790264541a}} 
\index{Ports@{Ports}!mmal\+\_\+port\+\_\+parameter\+\_\+get@{mmal\+\_\+port\+\_\+parameter\+\_\+get}}
\index{mmal\+\_\+port\+\_\+parameter\+\_\+get@{mmal\+\_\+port\+\_\+parameter\+\_\+get}!Ports@{Ports}}
\subsubsection{\texorpdfstring{mmal\+\_\+port\+\_\+parameter\+\_\+get()}{mmal\_port\_parameter\_get()}}
{\footnotesize\ttfamily \mbox{\hyperlink{group___mmal_types_ga5ac87230bd615d2b154a9d5899bc37fd}{M\+M\+A\+L\+\_\+\+S\+T\+A\+T\+U\+S\+\_\+T}} mmal\+\_\+port\+\_\+parameter\+\_\+get (\begin{DoxyParamCaption}\item[{\mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} $\ast$}]{port,  }\item[{\mbox{\hyperlink{struct_m_m_a_l___p_a_r_a_m_e_t_e_r___h_e_a_d_e_r___t}{M\+M\+A\+L\+\_\+\+P\+A\+R\+A\+M\+E\+T\+E\+R\+\_\+\+H\+E\+A\+D\+E\+R\+\_\+T}} $\ast$}]{param }\end{DoxyParamCaption})}

Get a parameter from a port. The size field must be set on input to the maximum size of the parameter (including the header) and will be set on output to the actual size of the parameter retrieved.

\begin{DoxyNote}{Note}
If M\+M\+A\+L\+\_\+\+E\+N\+O\+S\+PC is returned, the parameter is larger than the size given. The given parameter will have been filled up to its size and then the size field set to the full parameter\textquotesingle{}s size. This can be used to resize the parameter buffer so that a second call should succeed.
\end{DoxyNote}

\begin{DoxyParams}{Parameters}
{\em port} & The port to which the request is sent. \\
\hline
{\em param} & The pointer to the header of the parameter to get. \\
\hline
\end{DoxyParams}
\begin{DoxyReturn}{Returns}
M\+M\+A\+L\+\_\+\+S\+U\+C\+C\+E\+SS on success 
\end{DoxyReturn}
\mbox{\Hypertarget{group___mmal_port_ga7feccb996f0bab5c798b3465747bb0a3}\label{group___mmal_port_ga7feccb996f0bab5c798b3465747bb0a3}} 
\index{Ports@{Ports}!mmal\+\_\+port\+\_\+parameter\+\_\+set@{mmal\+\_\+port\+\_\+parameter\+\_\+set}}
\index{mmal\+\_\+port\+\_\+parameter\+\_\+set@{mmal\+\_\+port\+\_\+parameter\+\_\+set}!Ports@{Ports}}
\subsubsection{\texorpdfstring{mmal\+\_\+port\+\_\+parameter\+\_\+set()}{mmal\_port\_parameter\_set()}}
{\footnotesize\ttfamily \mbox{\hyperlink{group___mmal_types_ga5ac87230bd615d2b154a9d5899bc37fd}{M\+M\+A\+L\+\_\+\+S\+T\+A\+T\+U\+S\+\_\+T}} mmal\+\_\+port\+\_\+parameter\+\_\+set (\begin{DoxyParamCaption}\item[{\mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} $\ast$}]{port,  }\item[{const \mbox{\hyperlink{struct_m_m_a_l___p_a_r_a_m_e_t_e_r___h_e_a_d_e_r___t}{M\+M\+A\+L\+\_\+\+P\+A\+R\+A\+M\+E\+T\+E\+R\+\_\+\+H\+E\+A\+D\+E\+R\+\_\+T}} $\ast$}]{param }\end{DoxyParamCaption})}

Set a parameter on a port.


\begin{DoxyParams}{Parameters}
{\em port} & The port to which the request is sent. \\
\hline
{\em param} & The pointer to the header of the parameter to set. \\
\hline
\end{DoxyParams}
\begin{DoxyReturn}{Returns}
M\+M\+A\+L\+\_\+\+S\+U\+C\+C\+E\+SS on success 
\end{DoxyReturn}
\mbox{\Hypertarget{group___mmal_port_ga24fe58a6e95a5d69f79e1b69a601b714}\label{group___mmal_port_ga24fe58a6e95a5d69f79e1b69a601b714}} 
\index{Ports@{Ports}!mmal\+\_\+port\+\_\+payload\+\_\+alloc@{mmal\+\_\+port\+\_\+payload\+\_\+alloc}}
\index{mmal\+\_\+port\+\_\+payload\+\_\+alloc@{mmal\+\_\+port\+\_\+payload\+\_\+alloc}!Ports@{Ports}}
\subsubsection{\texorpdfstring{mmal\+\_\+port\+\_\+payload\+\_\+alloc()}{mmal\_port\_payload\_alloc()}}
{\footnotesize\ttfamily uint8\+\_\+t$\ast$ mmal\+\_\+port\+\_\+payload\+\_\+alloc (\begin{DoxyParamCaption}\item[{\mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} $\ast$}]{port,  }\item[{uint32\+\_\+t}]{payload\+\_\+size }\end{DoxyParamCaption})}

Allocate a payload buffer. This allows a client to allocate memory for a payload buffer based on the preferences of a port. This for instance will allow the port to allocate memory which can be shared between the host processor and videocore.

See \mbox{\hyperlink{group___mmal_pool_ga20230c4fff4a8db01fd5f8ae85bc685a}{mmal\+\_\+pool\+\_\+create\+\_\+with\+\_\+allocator()}}.


\begin{DoxyParams}{Parameters}
{\em port} & Port responsible for allocating the memory. \\
\hline
{\em payload\+\_\+size} & Size of the payload buffer which will be allocated.\\
\hline
\end{DoxyParams}
\begin{DoxyReturn}{Returns}
Pointer to the allocated memory. 
\end{DoxyReturn}
\mbox{\Hypertarget{group___mmal_port_gac130ad58018b781b0522a015bd243801}\label{group___mmal_port_gac130ad58018b781b0522a015bd243801}} 
\index{Ports@{Ports}!mmal\+\_\+port\+\_\+payload\+\_\+free@{mmal\+\_\+port\+\_\+payload\+\_\+free}}
\index{mmal\+\_\+port\+\_\+payload\+\_\+free@{mmal\+\_\+port\+\_\+payload\+\_\+free}!Ports@{Ports}}
\subsubsection{\texorpdfstring{mmal\+\_\+port\+\_\+payload\+\_\+free()}{mmal\_port\_payload\_free()}}
{\footnotesize\ttfamily void mmal\+\_\+port\+\_\+payload\+\_\+free (\begin{DoxyParamCaption}\item[{\mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} $\ast$}]{port,  }\item[{uint8\+\_\+t $\ast$}]{payload }\end{DoxyParamCaption})}

Free a payload buffer. This allows a client to free memory allocated by a previous call to \mbox{\hyperlink{group___mmal_port_ga24fe58a6e95a5d69f79e1b69a601b714}{mmal\+\_\+port\+\_\+payload\+\_\+alloc}}.

See \mbox{\hyperlink{group___mmal_pool_ga20230c4fff4a8db01fd5f8ae85bc685a}{mmal\+\_\+pool\+\_\+create\+\_\+with\+\_\+allocator()}}.


\begin{DoxyParams}{Parameters}
{\em port} & Port responsible for allocating the memory. \\
\hline
{\em payload} & Pointer to the memory to free. \\
\hline
\end{DoxyParams}
\mbox{\Hypertarget{group___mmal_port_ga098a7b91bb6fc596aed0e5585aee3253}\label{group___mmal_port_ga098a7b91bb6fc596aed0e5585aee3253}} 
\index{Ports@{Ports}!mmal\+\_\+port\+\_\+send\+\_\+buffer@{mmal\+\_\+port\+\_\+send\+\_\+buffer}}
\index{mmal\+\_\+port\+\_\+send\+\_\+buffer@{mmal\+\_\+port\+\_\+send\+\_\+buffer}!Ports@{Ports}}
\subsubsection{\texorpdfstring{mmal\+\_\+port\+\_\+send\+\_\+buffer()}{mmal\_port\_send\_buffer()}}
{\footnotesize\ttfamily \mbox{\hyperlink{group___mmal_types_ga5ac87230bd615d2b154a9d5899bc37fd}{M\+M\+A\+L\+\_\+\+S\+T\+A\+T\+U\+S\+\_\+T}} mmal\+\_\+port\+\_\+send\+\_\+buffer (\begin{DoxyParamCaption}\item[{\mbox{\hyperlink{struct_m_m_a_l___p_o_r_t___t}{M\+M\+A\+L\+\_\+\+P\+O\+R\+T\+\_\+T}} $\ast$}]{port,  }\item[{\mbox{\hyperlink{struct_m_m_a_l___b_u_f_f_e_r___h_e_a_d_e_r___t}{M\+M\+A\+L\+\_\+\+B\+U\+F\+F\+E\+R\+\_\+\+H\+E\+A\+D\+E\+R\+\_\+T}} $\ast$}]{buffer }\end{DoxyParamCaption})}

Send a buffer header to a port.


\begin{DoxyParams}{Parameters}
{\em port} & The port to which the buffer header is to be sent. \\
\hline
{\em buffer} & The buffer header to send. \\
\hline
\end{DoxyParams}
\begin{DoxyReturn}{Returns}
M\+M\+A\+L\+\_\+\+S\+U\+C\+C\+E\+SS on success 
\end{DoxyReturn}
